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Faculty Staff |
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Phone: (850) 833-9381 (REEF)
Current ProjectsRecent work has been done to automate the partitioning algorithm and to improve it, leading to the development of the I-PIFAN algorithm where the effect of critical path, testing time and added hardware have been incorporated into the partitioning process. A pending proposal was submitted to implement the I-PIFAN Algorithm into a physical VLSI integrated chip and to incorporate a built-in self-test architecture. Research InterestsMy research field is in VLSI design, testing, partitioning and Built-in Self-Test. I have developed a new partitioning algorithm, which facilitates pseudo-exhaustive testing of VLSI digital circuits. This algorithm is based on an analysis of a circuit's Primary Input cones and FANout values (PIFAN), and it uses a directed acyclic graph to represent the circuit. An invasive approach is employed which creates logical and physical partitions by inserting reconfigurable test cells and multiplexers. The test cells are used to control and observe multiple partitioning points, while the multiplexers expand the controllability and observability provided by the test cells. The feasibility and efficiency of algorithm are evaluated by partitioning numerous standard digital circuits, including some large benchmark circuits. The results show that the PIFAN algorithm offers significant reductions in overhead and test time when compared to previous partitioning algorithms. In addition, the algorithm is based upon pseudo-exhaustive testing methods and fault simulation and is not required for test pattern generation and grading; hence, engineering design time and cost are further reduced. |
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